Tutorial 4: Timer0 Counter mode falling T0CKI with Prescalar

In Timer0 mode counter mode, the TMR0 register increments on either a rising or falling edge of a clock cycle. This tutorial demonstrates the use of Counter Mode, with prescalar incrementing on the falling edge of an external clock generated by a 555 Timer.

Download FEATURE7X_Tutorial4.zip and unzip into folder <your path>\Tutorial 4

Filename Version Description
tut4.pjt 1.0 MPLAB Project
tut4.asm 1.0 Assembler code
tut4.hex 1.0 Precompiled HEX
tut4.lst 1.0 Precompiled LST
tut4.vbb 1.0 Virtual Breadboard simulation

Running the Simulation

Open tut4.vbb and press RUN.

Code Walk Through

Features Demonstrated

TRISB/PORTB

TIMER0 Counter Mode Falling T0KI Edge

TIMER0 prescalar

Components Used

PIC16C71

PIC16C715

LED8

555 TIMER

NET LABEL