Tutorial 11: Beware TMR0 write 2 Cycle Inhibit, Prescalar clear!

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Any instruction that writes to the TMR0 has will inhibit the TMR0 increment and will clear the prescalar. This can have unexpected results when calculating timings.

Description

Download FEATURE877_Tutorial11.zip and unzip into folder <your path>\Tutorial 11

Filename Version Description
tut11.pjt 1.0 MPLAB (2.3) Project
tut11.asm 1.0 PIC16F877 Assembler code
tut11.hex 1.0 Precompiled HEX
tut11.lst 1.0 Precompiled LST
tut11.vbb 1.0 Virtual Breadboard simulation

 

Demonstrates

Timer0 2 cycle Inhibit on write

Prescalar clear on write